Re: [myhdl-list] Restrictions for conversion

[Jan D. <ja...@ja...>]

On 05/23/2012 12:47 PM, Christopher Felton wrote:

>>
>>> Norbo prototyped this and it all seemed good but we have been discussing
>>> the overall behavior.  I think this is where we sit right now.
>>>
>>>        1.  Initial value support should be added, it resolves
>>>            the time 0 mismatch.  It has been verified with
>>>            the latest versions of Quartus and ISE.
>>
>> Yes.
>
> The one implementation detail we ran into, was that the continuous
> assign statements in Verilog will need to be replaced with an @always block.

Ok, I see, I glanced over the discussions between Norbo and you.

A word of caution though: there are subtle semantic differences
between assign, always(*) and always_comb in Verilog.

I *think* always_comb should be ok, after all I once modeled
it in MyHDL after this.

Several new issues arise: do all synthesis tools that we target
(also the free ones from X/A) support always_comb, which is
basically a SystemVerilog construct? And if they do, do they
support it in a template for RAM inference?

A prudent way forward initially might be to add the initialization
only to what is currently converted as a reg.

Jan

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