Re: [myhdl-list] Restrictions for conversion

[Jan D. <ja...@ja...>]

On 05/23/2012 04:37 AM, Christopher Felton wrote:
> On 5/22/12 4:32 PM, Jan Decaluwe wrote:
>> On 05/22/2012 05:34 PM, Christopher Felton wrote:
>>
>>>
>>> FPGAs support pre-init RAM.  Synthesis will extract the array initial
>>> values from the HDL and during configuration program the BRAM (internal
>>> FPGA RAM).  When the FPGA comes out of reset (not logic reset, FPGA post
>>> config reset) the RAM will contain the initial values.  The RAM is a RAM
>>> so the values can be overridden by the logic, i.e not a ROM.  This is
>>> only possible in an FPGA and is supported by X&A synthesis tools.
>>>
>>> I don't know a reasonable method to achieve the pre-init RAM, currently.
>>
>> Do you mean no reasonable method from MyHDL, or no reasonable method
>> at all?
>
> That was somewhat missed phrased, "... reasonable method ...".
> Currently initial values are not supported (enabled), for basic types or
> arrays (memories).  Currently you cannot do either.  I should have
> said, pre-init RAM is not supported in MyHDL.
>
> Known, reasonable, RAM pre-init methods are available for Verilog/VHDL.
>    It seems reasonable to include with the initial value support.

Yes. Now, from the altera literature it seems they also support
$readmemb, which would make it possible to initialize a RAM with
arbitrary values. But I don't know how to do that with VHDL.

Would it be sufficient to support memory initialization to
an identical value for each location?

> Norbo prototyped this and it all seemed good but we have been discussing
> the overall behavior.  I think this is where we sit right now.
>
>      1.  Initial value support should be added, it resolves
>          the time 0 mismatch.  It has been verified with
>          the latest versions of Quartus and ISE.

Yes.

>      2.  Intial value support for arrays should be included
>          (all types are initialized).  Verdict is still out
>          if the ivs for arrays should be "synthesizable".

Yes.

In summary: I think initial values should be written, regardless of
what synthesis does with it, because of the exact match in
simulation.


>      3.  Unresolved, should there be a method to disable
>          ivs.  The current proposed method is to use None.

As a fallback method, I think it would be wise to be able
to disable initial value writing by a control parameter
to toVerilog/toVHDL. A separate control for plain signals
and arrays probably. But this would be purely because some
synthesis tools may not support the syntax.

I don't see a value in adding support for None to intbv,
as discussed before.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com