Re: [myhdl-list] Restrictions for conversion

[Christopher F. <chr...@gm...>]

On 5/22/12 4:32 PM, Jan Decaluwe wrote:
> On 05/22/2012 05:34 PM, Christopher Felton wrote:
>
>>
>> FPGAs support pre-init RAM.  Synthesis will extract the array initial
>> values from the HDL and during configuration program the BRAM (internal
>> FPGA RAM).  When the FPGA comes out of reset (not logic reset, FPGA post
>> config reset) the RAM will contain the initial values.  The RAM is a RAM
>> so the values can be overridden by the logic, i.e not a ROM.  This is
>> only possible in an FPGA and is supported by X&A synthesis tools.
>>
>> I don't know a reasonable method to achieve the pre-init RAM, currently.
>
> Do you mean no reasonable method from MyHDL, or no reasonable method
> at all?
>
> And if there is a reasonable method, how does it work?
>

Didn't include the reference, for Quartus the pre-init RAM templates can 
be found in the following.

http://www.altera.com/literature/hb/qts/qts_qii51007.pdf

Regards,
Chris