Re: [myhdl-list] Restrictions for conversion

[Christopher F. <chr...@gm...>]

On 5/22/12 4:32 PM, Jan Decaluwe wrote:
> On 05/22/2012 05:34 PM, Christopher Felton wrote:
>
>>
>> FPGAs support pre-init RAM.  Synthesis will extract the array initial
>> values from the HDL and during configuration program the BRAM (internal
>> FPGA RAM).  When the FPGA comes out of reset (not logic reset, FPGA post
>> config reset) the RAM will contain the initial values.  The RAM is a RAM
>> so the values can be overridden by the logic, i.e not a ROM.  This is
>> only possible in an FPGA and is supported by X&A synthesis tools.
>>
>> I don't know a reasonable method to achieve the pre-init RAM, currently.
>
> Do you mean no reasonable method from MyHDL, or no reasonable method
> at all?

That was somewhat missed phrased, "... reasonable method ...". 
Currently initial values are not supported (enabled), for basic types or 
arrays (memories).  Currently you cannot do either.  I should have 
said, pre-init RAM is not supported in MyHDL.

Known, reasonable, RAM pre-init methods are available for Verilog/VHDL. 
  It seems reasonable to include with the initial value support.

Norbo prototyped this and it all seemed good but we have been discussing 
the overall behavior.  I think this is where we sit right now.

    1.  Initial value support should be added, it resolves
        the time 0 mismatch.  It has been verified with
        the latest versions of Quartus and ISE.

    2.  Intial value support for arrays should be included
        (all types are initialized).  Verdict is still out
        if the ivs for arrays should be "synthesizable".

    3.  Unresolved, should there be a method to disable
        ivs.  The current proposed method is to use None.


>
> And if there is a reasonable method, how does it work?
>

For Verilog it is an initial block, like the following

     initial begin
         for (i = 0; i < 32; i = i + 1)
             mem[i] = i[7:0];
     end

VHDL it is similar but uses a function,

     TYPE MEM IS ARRAY(31 DOWNTO 0) OF unsigned(7 DOWNTO 0);
     FUNCTION initialize_ram
         return MEM is
         variable result : MEM;
     BEGIN
         FOR i IN 31 DOWNTO 0 LOOP
             result(i) := to_unsigned(natural(i), natural'(8));
         END LOOP;
         RETURN result;
    END initialize_ram;

What I don't recall (what needs to be verified) if the above "templates" 
are supported by most synthesis tools, pretty sure simulation will 
support the above for arrays (memories).

Regards,
Chris