Re: [myhdl-list] Restrictions for conversion

[Jan D. <ja...@ja...>]

On 05/22/2012 05:34 PM, Christopher Felton wrote:

>
> FPGAs support pre-init RAM.  Synthesis will extract the array initial
> values from the HDL and during configuration program the BRAM (internal
> FPGA RAM).  When the FPGA comes out of reset (not logic reset, FPGA post
> config reset) the RAM will contain the initial values.  The RAM is a RAM
> so the values can be overridden by the logic, i.e not a ROM.  This is
> only possible in an FPGA and is supported by X&A synthesis tools.
>
> I don't know a reasonable method to achieve the pre-init RAM, currently.

Do you mean no reasonable method from MyHDL, or no reasonable method
at all?

And if there is a reasonable method, how does it work?



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Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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