Re: [myhdl-list] Restrictions for conversion

[Norbo <Nor...@gm...>]

Am 22.05.2012, 15:16 Uhr, schrieb Jan Decaluwe <ja...@ja...>:

> On 05/05/2012 05:20 PM, Norbo wrote:
>
>> another point is that i think it is a good thing to have all the  
>> variables
>> by default not to be initialized
>> with values in the converted code. Initialisation should only occour if
>> you really want to describe (pre-init RAM)
>> or ROM.
>> because for example in VHDL all the std_logic signals are set at startup
>> of a vhdl simulation to the value 'U' (stands for uninitialized) if  
>> there
>> is no other initial value given. After the reset all values should have
>> changed from this
>> 'U' to something usefull. This allows you to see imidiatly if you have
>> messed up or missed something in the reset code.
>
> No, you don't see it immediately. You have to fire up a simulation,
> and then be lucky that the problem is not masked by logical
> operations.

obviously there is no way around the simulation at least for setting the  
reset for some time
to low and then to high.
What you forget is that the reset is asynchron, so the normal flip-flop  
operation is "blocked" and no logical
masking or whatsoever will occour. You dont even have to apply a clock  
signal to see it.


> For something like this, I think the only good way is a formal
> check. What I always use is a simple check of flip-flop types
> inferred by synthesis. Works like a charm, no simulation needed,
> and you catch everything in one pass.

Yeah, you can do that but, i personally dont like two wait till the end of  
a e.g: "hour" long synthesis to
just discover that something is wrong with reset values and than synthesis  
all over again.


greetings
Norbo