Re: [myhdl-list] Restrictions for conversion

[Christopher F. <chr...@gm...>]

On 5/22/2012 8:51 AM, Jan Decaluwe wrote:
> On 05/22/2012 03:29 PM, Tom Dillon wrote:
>> On 05/22/2012 08:12 AM, Jan Decaluwe wrote:
>>> On 05/05/2012 05:20 PM, Norbo wrote:
>>>
>>>
>>>> another point is that i think it is a good thing to have all the variables
>>>> by default not to be initialized
>>>> with values in the converted code.
>>> No, they should, for the simple reason that the intent of conversion
>>> is to generate Verilog/VHDL which matches the MyHDL behavior exactly.
>>>
>>> The only reason why they are not written currently (once they were) is
>>> a practical one: some synthesis tools didn't support this. But as soon
>>> we are sure they all do, I will want to change that. That would solve all
>>> kinds of issues at simulation time 0.
>>
>> It can be annoying not to have a value at time 0 since you can get some
>> warnings but I don't think all synthesis tools will take care of this
>> for you. Depending on what you are synthesizing to it might not even be
>> possible.
>
> I am not saying synthesis should do anything with these values. It
> should just support the syntax.
>
> What this gives us is that at least in simulation, we would get a full
> match between MyHDL and the converted Verilog/VHDL, which is the
> primary goal of conversion. Now we sometimes don't at time 0, and it's
> always confusing.
>
>> I think the only way to guarantee initial values is the have a set/reset
>> that is activated and use it in your logic to properly initialize
>> anything that matters.
>
> At the gate level, of course.
>
>> Now maybe we are trying to deal with special cases in FPGAs? Such as
>> initializing memory? I am coming late to this discussion.
>
> Me also :-) I would also like to hear a simple explanation of this.
>
>

You had to add the "simple" qualifier :)

FPGAs support pre-init RAM.  Synthesis will extract the array initial 
values from the HDL and during configuration program the BRAM (internal 
FPGA RAM).  When the FPGA comes out of reset (not logic reset, FPGA post 
config reset) the RAM will contain the initial values.  The RAM is a RAM 
so the values can be overridden by the logic, i.e not a ROM.  This is 
only possible in an FPGA and is supported by X&A synthesis tools.

I don't know a reasonable method to achieve the pre-init RAM, currently. 
  Theoretically, this would be supported with initial value support; 
such that the lower HDL matches the MyHDL at time 0.  I don't see a 
reason why the memory initial value shouldn't be synthesizable, as well, 
if the tools support it.

The question is for large memories would you want to be able to disable 
initial values for the memory array?  Would the overhead in simulation 
and/or synthesis be too costly to always include the memory initial values?

And yes, we should have some information on the cost of large memory 
initial values before proclaiming we need a method to disable.  I have 
not run any experiments or run into this in the past.  Anyone have any 
data points if large pre-init RAM structures are costly in simulation or 
synthesis?

Summary, two items.  One synthesizable initial value support (ivs) for 
RAM memories.  Second, does there need to be a method to disable ivs for 
RAM memories?

Regards,
Chris