Re: [myhdl-list] Restrictions for conversion

[Tom D. <td...@di...>]

On 05/22/2012 08:12 AM, Jan Decaluwe wrote:
> On 05/05/2012 05:20 PM, Norbo wrote:
>
>
>> another point is that i think it is a good thing to have all the variables
>> by default not to be initialized
>> with values in the converted code.
> No, they should, for the simple reason that the intent of conversion
> is to generate Verilog/VHDL which matches the MyHDL behavior exactly.
>
> The only reason why they are not written currently (once they were) is
> a practical one: some synthesis tools didn't support this. But as soon
> we are sure they all do, I will want to change that. That would solve all
> kinds of issues at simulation time 0.

It can be annoying not to have a value at time 0 since you can get some 
warnings but I don't think all synthesis tools will take care of this 
for you. Depending on what you are synthesizing to it might not even be 
possible.

I think the only way to guarantee initial values is the have a set/reset 
that is activated and use it in your logic to properly initialize 
anything that matters.

Now maybe we are trying to deal with special cases in FPGAs? Such as 
initializing memory? I am coming late to this discussion.