Re: [myhdl-list] Restrictions for conversion

[Jan D. <ja...@ja...>]

On 05/05/2012 05:20 PM, Norbo wrote:

> another point is that i think it is a good thing to have all the variables
> by default not to be initialized
> with values in the converted code. Initialisation should only occour if
> you really want to describe (pre-init RAM)
> or ROM.
> because for example in VHDL all the std_logic signals are set at startup
> of a vhdl simulation to the value 'U' (stands for uninitialized) if there
> is no other initial value given. After the reset all values should have
> changed from this
> 'U' to something usefull. This allows you to see imidiatly if you have
> messed up or missed something in the reset code.

No, you don't see it immediately. You have to fire up a simulation,
and then be lucky that the problem is not masked by logical
operations.

For something like this, I think the only good way is a formal
check. What I always use is a simple check of flip-flop types
inferred by synthesis. Works like a charm, no simulation needed,
and you catch everything in one pass.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
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