Re: [myhdl-list] Restrictions for conversion

[Jan D. <ja...@ja...>]

On 05/05/2012 05:20 PM, Norbo wrote:


> another point is that i think it is a good thing to have all the variables
> by default not to be initialized
> with values in the converted code.

No, they should, for the simple reason that the intent of conversion
is to generate Verilog/VHDL which matches the MyHDL behavior exactly.

The only reason why they are not written currently (once they were) is
a practical one: some synthesis tools didn't support this. But as soon
we are sure they all do, I will want to change that. That would solve all
kinds of issues at simulation time 0.

> The point is, by default no initial value should be written in the
> converted code, only when you need it explicit to describe something.
> Maybe a default None value in the intbv?

If you do something special for the intbv, then that can only give
a half-hearted solution. I would like to encourage the use of high-level
types such as bool and enum.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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