Re: [myhdl-list] MEP : Signal Containers

[Norbo <Nor...@gm...>]

My idea is to bring it together:

So one proposal is to add conversion support for functions inside a class  
like this:
-------------------------------
class Adder():
    def __init__(self):
       pass
    def hdl(self, x, y, z):
       @always_comb
       def _hdl():
          z.next = x + y
       return _hdl
...
...
toVerilog(adder, x, y, z)
toVHDL(adder, x, y, z)
-------------------------------
to do this the self argument needs to be ignored in the conversion


The other proposal seems to be, using classes as signal container.
like previously posted:
-----------------------------------------
      class WishboneBus(object):
          def __init__(self, DataWidth=16, AddressWidth=8):
              self.clk = Signal(False)
              self.rst = Signal(False)
              self.cyc = Signal(False)
              self.stb = Signal(False)
              self.adr = Signal(intbv(0)[AddressWeidth:])
              self.dat_i = Signal(intbv(0)[DataWidth:])
              self.dat_o = Signal(intbv(0)[DataWidth:])
              self.we = Signal(False)
              self.sel = Signal(intbv(0)[int(DataWidth/8)"])
              self.ack = Signal(False)

      def WbGpio(wb_bus, outs, ints):
	...

      wb_bus = WishboneBus()
      outs = Signal(intbv(0)[8:])
      ints = Signal(intbv(0)[8:])
      iGpio = WbGpio(wb_bus, outs, ins)

And for conversion:
      toVHDL(WbGpio, wb_bus, outs, ins)  ### here the class signals are  
added to the port in the conversion
-----------------------------------------------------
there all the class internal signals are added to the port in the  
conversion.
What if the "self" is accepted as a class instance and every signal of it  
is written in the conversion as a port signal also
Becaus then it is probably posible to write Whisbone pheriperials like  
this:

      class WishboneBus(object):
          def __init__(self, DataWidth=16, AddressWidth=8):
              self.clk = Signal(False)
              self.rst = Signal(False)
              self.cyc = Signal(False)
              self.stb = Signal(False)
              self.adr = Signal(intbv(0)[AddressWeidth:])
              self.dat_i = Signal(intbv(0)[DataWidth:])
              self.dat_o = Signal(intbv(0)[DataWidth:])
              self.we = Signal(False)
              self.sel = Signal(intbv(0)[int(DataWidth/8)"])
              self.ack = Signal(False)

      class WbPheripherialClass(WishboneBus)  ### inherits all signals from  
WishbonBus
	 def WbGpio(self,outs, ints):   ### the self stand for all the WishbonBus  
signals
              @always_comb
	     def .......

	 def WbRS232(self,iRX, oTX):
		.....	

	

     Wbobj=WbPheripherialClass()
     toVHDL(Wbobj.WbGpio, outs, ins)  ### all signals in the "self" are  
also inserted into the port in the conversion.

or that if you instanciate them:

     outs = Signal(intbv(0)[8:])
     ints = Signal(intbv(0)[8:])
     iRX = Signal(bool(0))
     oTX = Signal(bool(0))
     Wbobj=WbPheripherialClass()
     Gpio_inst=Wbobj.WbGpio(outs,ints)
     RS232_inst=Wbobj.WbRS232(iRX,oTX)

so that all the shared signals are magically connected and writing to the  
signals maybe could be done by:
     Wbobj.clk.next=1


No this is not really thought through or confusing.
anyway:

greetings
Norbo