Re: [myhdl-list] Bernd Paysan's b16 processor in MyHDL

[Jan C. <jan...@mu...>]

On 19/05/12 12:41, Christopher Lozinski wrote:
> It looks like you have made huge process on this device.  Not only in
> MyHDL, but also in forth.   Congratulations on the hard work.
Not mine!  Credits appear in sources.

> I like that you list the components, RAM, CPU, Stack, ALU.  Goes a long
> way to explaining what you have built. Of course code is always painful
> to read through, English high level description is always easier and
> faster to read.  The article on a forth processor in FPGA looks hugely
> interesting.  What is your relationship with the author?
Bernd rides what I dreamed of as a boy.  I just split his code into 
separate files, and expanded the signal names so it would be easier 
for you to read.

> I did not understand the table at the top of [Bernd's] web page.  What are
> the horizontal and vertical axes?
This is the instruction set matrix, but there is a much clearer one 
in the MyHDL source file.

> So let me ask the obvious marketing questions.  How many transistors are
> in this device?  How many in the 8051?  Better yet, how many in each
> component, where did you shrink it the most?   And how many instructions
> per second can each execute.   Which component slows you down the most?
> Obviously this is on a FPGA, the other on silicon, so one needs to scale
> between them.
Bernd has used this [2] in silicon, but, as I have no access to 
silicon I do not know.  Because the instruction set is unusual, you 
would need to test with some real code; give it a try.

> Many many years ago, Marvin Minsky, an AI professor at MIT tried to
> build a slower cpu.  A bit embarrassing.  He does not talk about it very
> much.  But a smaller, more power and space efficient cpu is a great idea.
I recently heard that the wiring in the brain is like layers of 
matting, providing X & Y axis fibers, with Z axis fibers 
penetrating the layers of matting. [1]  Having a large number of 
simpler slower processors is no problem if you have massive 
interconnect, and superb organisational skills.

> So how much better is this device?  Of course the real test are the
> benchmarks.
Yes, you could start with just the hardware description in MyHDL, 
and test a few instructions, then move on to using the cross 
development tools.  Any documentation shortages we could make up 
between us.

It would be good to get interactive code development working using 
the cross-dev tools and the MyHDL model.  Then you could choose 
some simple jobs, and get benchmarking.

Jan Coombs
-- 
[1] http://www.nsf.gov/news/news_images.jsp?cntn_id=123711&org=NSF
[2] http://bernd-paysan.de/b16.html