Re: [myhdl-list] Example of MyHDL for Python Developers Documentation

[Christopher F. <chr...@gm...>]

On 5/18/12 6:57 PM, Jan Coombs wrote:
> On 18/05/12 22:32, Christopher Felton wrote:
>      . . .
>> This whole tangent on async FPGA hasn't been that useful.
>
> No, sorry.  It was intended to be an empathetic illustration to
> show that there is an optimum depth of hardware appreciation for
> effective RTL design.
>
> Jan Coombs.
>

Jan C.

I didn't mean any offensive by this.  I thought the "async" comments 
were a reference to an off-topic conversation about Achronix FPGAs in 
this thread?  But it wasn't, the async FPGA was brought up in a separate 
thread and was more applicable in the other context.  I had simply 
merged these two threads in my mind making them non-coherent, which was 
*not* the case.

I think your description on how flexible MyHDL can be was useful.  My 
comment was out of context, sorry about that.

Regards,
Chris Felton