Re: [myhdl-list] Example of MyHDL for Python Developers Documentation

[Christopher F. <chr...@gm...>]

On 5/18/12 8:13 PM, Christopher Lozinski wrote:
> On 5/18/12 6:57 PM, Jan Coombs wrote:
>> On 18/05/12 22:32, Christopher Felton wrote:
>>      . . .
>>> This whole tangent on async FPGA hasn't been that useful.
>> No, sorry.  It was intended to be an empathetic illustration to
>> show that there is an optimum depth of hardware appreciation for
>> effective RTL design.
>>
>> Jan Coombs.
>>
> I loved Jan C's question.   I learned a lot from it.  He is also buiding
> great stuff, if I get it correctly, minimal space adders and other
> components.  That is an important set of ideas to include in this
> group.  He is one of only two or three guys working on cpu's.  And the
> whole idea of getting away from a central clock, to everything running
> at its own speed, I believe can lead to vast speed improvements.   In
> particular it helped me really understand that there can be different
> high level models of the same digital component, based on how it is used.

I might be getting confused here, this was a long thread.  But what was 
the question Jan C. asked?  Maybe you, Christopher L,  can refresh my 
memory for me and remind what the question Jan C. asked was?

Regards,
Chris Felton