Re: [myhdl-list] Example of MyHDL for Python Developers Documentation

[Christopher L. <loz...@fr...>]

On 5/18/12 6:57 PM, Jan Coombs wrote:
> On 18/05/12 22:32, Christopher Felton wrote:
>     . . .
>> This whole tangent on async FPGA hasn't been that useful.
> No, sorry.  It was intended to be an empathetic illustration to 
> show that there is an optimum depth of hardware appreciation for 
> effective RTL design.
>
> Jan Coombs.
>
I loved Jan C's question.   I learned a lot from it.  He is also buiding
great stuff, if I get it correctly, minimal space adders and other
components.  That is an important set of ideas to include in this
group.  He is one of only two or three guys working on cpu's.  And the
whole idea of getting away from a central clock, to everything running
at its own speed, I believe can lead to vast speed improvements.   In
particular it helped me really understand that there can be different
high level models of the same digital component, based on how it is used. 

Let us lighten up a little bit.  And embrace all the wonderful ideas
that this group of people have.  Let us face it, we are not mainstream
digital circuit designers.  There are some very interesting ideas
floating around.  I love Dillon's examples of  Hierarchical signals,
complex numbers.  I love the idea of building a python processor. 

You are all a very smart bunch of people.  As one person said, we post
ideas to stimulate others thinking.  Hopefully this is not just about
existing MyHDL, but about the dreams of where digital circuit design can
go. I am hugely stimulated by this group.  I have certainly done my
share of stimulating the conversation.    Please keep it up Jan C. . 

Chris L.