Re: [myhdl-list] Example of MyHDL for Python Developers Documentation

[Jan C. <jan...@mu...>]

On 18/05/12 22:32, Christopher Felton wrote:
    . . .
> This whole tangent on async FPGA hasn't been that useful.

No, sorry.  It was intended to be an empathetic illustration to 
show that there is an optimum depth of hardware appreciation for 
effective RTL design.

Jan Coombs.