Re: [myhdl-list] Example of MyHDL for Python Developers Documentation

[Christopher F. <chr...@gm...>]

On 5/16/12 7:54 AM, Jan Coombs wrote:
> On 16/05/12 12:58, Oscar Diaz wrote:
>      . . . [big snip]
>>
>> What I wanted to say is that Christopher's proposal maybe is not
>> suitable for all cases, and IMHO one of the strengths of MyHDL is that
>> it doesn't tie you to a particular way to describe your objects at
>> high level, the only condition is that you provide a list of
>> generators and signals that link them, but you can use whatever you
>> want to create them.
>
> If Chris L. wants a higher level of abstraction, this will likely
> still depend on tools to describe RTL, for example MyHDL.
> Suggesting that this might be an extension, or revised expression
> method for MyHDL is incorrect, because it, like IP modules, is not
> expressed at the same level of abstraction.

I think this is a point often missed.  If you look at it as a tool stack 
there probably will be multiple packages for this magical VHL 
(very-high-level) hardware description/conversion package and MyHDL will 
be an important package in the stack.  But something outside the MyHDL 
goals would probably be required.  I say outside the MyHDL goals because 
I think the VHL-DH will have many constraints where MyHDL like the other 
HDLs at similar abstractions levels are more general.

If you look at the other attempts this is what was being done.  Some 
projects provide means to connect things via streams (similar to the 
streams-C hdl).  And then created state-machines a certain way 
(sometimes using a cpu?), module connections, etc.  You traded possibly 
a simplified description for loss of implementation control.

>
>> The Hardware Module Class can be the base class of a particular set of
>> IP cores, but it shouldn't be part of core MyHDL. In this case, making
>> an analogy to software development, you could think this class as a
>> "library" that "programs" (IP cores) can use.
>
> Agreed, perhaps "Hardware Module Class" is misnamed?  RTLs like
> MyHDL express designs at an abstraction level significantly above
> hardware.

I lack the ability to see how the Hardware class thing is useful at all.

>
> Or maybe there is confusion; When showing interest in whether block
> RAMs in async logic chips are conventional RAMs in an async
> wrapper, or truly constructed from async logic, Chris L. suggested:
>
> "What is needed is a class called ClocklessGateArray, which you
> could just use, or read the code to see how it is modelled."

This whole tangent on async FPGA hasn't been that useful.  I missed what 
was trying to be achieved.  To use MyHDL on an Achronix FPGA, in that 
case nothing needs to be done just code away.  Or the interest to 
describe at a higher-level async logic.  If that latter see an older 
thread where this was discussed (a couple years ago).

Regards,
Chris