Re: [myhdl-list] Example of MyHDL for Python Developers Documentation

[Jan C. <jan...@mu...>]

On 16/05/12 12:58, Oscar Diaz wrote:
    . . . [big snip]
>
> What I wanted to say is that Christopher's proposal maybe is not
> suitable for all cases, and IMHO one of the strengths of MyHDL is that
> it doesn't tie you to a particular way to describe your objects at
> high level, the only condition is that you provide a list of
> generators and signals that link them, but you can use whatever you
> want to create them.

If Chris L. wants a higher level of abstraction, this will likely 
still depend on tools to describe RTL, for example MyHDL. 
Suggesting that this might be an extension, or revised expression 
method for MyHDL is incorrect, because it, like IP modules, is not 
expressed at the same level of abstraction.

> The Hardware Module Class can be the base class of a particular set of
> IP cores, but it shouldn't be part of core MyHDL. In this case, making
> an analogy to software development, you could think this class as a
> "library" that "programs" (IP cores) can use.

Agreed, perhaps "Hardware Module Class" is misnamed?  RTLs like 
MyHDL express designs at an abstraction level significantly above 
hardware.

Or maybe there is confusion; When showing interest in whether block 
RAMs in async logic chips are conventional RAMs in an async 
wrapper, or truly constructed from async logic, Chris L. suggested:

"What is needed is a class called ClocklessGateArray, which you 
could just use, or read the code to see how it is modelled."

This answer might/might-not be right, because, to write this class 
a person might/might-not choose to incorporate the information 
derived by answering my original question about RAMs in async gate 
array fabric.

Jan Coombs.