[myhdl-list] Object type is not supported in this context
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From: Jan C. <jan...@mu...> - 2012-05-12 13:03:24
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This error message points to a blank line, which is always immediately before the start of a code block: myhdl.ConversionError: File /home/jan/work/projects/MyHDL/SDP_3o4/work/sdp3o4.py, line 123: Object type is not supported in this context: ExST Does it refer to the next or previous block of code? I assumed that it would be the previous block of code, and commented out all lines referring to the state constants, but the error remains the same, even the line number. ExST = enum('Fetch1','Fetch2','NewAddr','Skip', \ 'Gap','Broken', encoding='one_hot') The next block of code would be difficult without the enum, but this seems to be where the problem is: @always_comb def execNextStateLogic_AsyncNoVar(): ''' determine what next execution state will be ''' ''' line 159: Object type is not supported in this context: ExST ''' if reset: execNextState.next = ExST.Skip else: if (execState==ExST.Fetch1): if (memRdSlice==ToMem)| \ (memRdSlice==Alu2op)| \ (memRdSlice==Alu1op)| \ (memRdSlice==FromMem): \ execNextState.next = ExST.Fetch2 elif (memRdSlice==Branch): \ execNextState.next = ExST.NewAddr elif (memRdSlice==Skip)| \ (memRdSlice==Lit)| \ (memRdSlice==Call): \ execNextState.next = ExST.Skip else: execNextState.next = ExST.Gap elif execState==ExST.Fetch2: \ execNextState.next = ExST.Gap elif execState==ExST.NewAddr: if (memRdMore==0): \ execNextState.next = ExST.Gap else: execNextState.next = ExST.NewAddr elif execState==ExST.Skip: if (memRdMore==0): \ execNextState.next = ExST.Gap elif execState==ExST.Gap: \ execNextState.next = ExST.Fetch1 elif execState==ExST.Broken: \ execNextState.next = ExST.Broken else: execNextState.next = ExST.Broken Now I have converted the code using enum to use constants, and don't get the improper use of ExST error. The simulation still looks ok, but I now get this: jan@T60:~/work/projects/MyHDL/SDP_3o4/work$ ./testSdp3o4.py <class 'myhdl._SuspendSimulation'>: Simulated 350 timesteps Traceback (most recent call last): File "./testSdp3o4.py", line 46, in <module> toVerilog(sdp3o4, clk,reset, addr, doSim) File "/home/jan/work/projects/MyHDL/myhdl/myhdl/conversion/_toVerilog.py", line 151, in __call__ _convertGens(genlist, vfile) File "/home/jan/work/projects/MyHDL/myhdl/myhdl/conversion/_toVerilog.py", line 374, in _convertGens v.visit(tree) File "/usr/lib/python2.7/ast.py", line 241, in visit return visitor(node) File "/home/jan/work/projects/MyHDL/myhdl/myhdl/conversion/_toVerilog.py", line 964, in visit_Module self.visit(stmt) File "/usr/lib/python2.7/ast.py", line 241, in visit return visitor(node) File "/home/jan/work/projects/MyHDL/myhdl/myhdl/conversion/_toVerilog.py", line 1285, in visit_FunctionDef self.visit_stmt(node.body) File "/home/jan/work/projects/MyHDL/myhdl/myhdl/conversion/_toVerilog.py", line 1141, in visit_stmt self.visit(stmt) File "/usr/lib/python2.7/ast.py", line 241, in visit return visitor(node) File "/home/jan/work/projects/MyHDL/myhdl/myhdl/conversion/_toVerilog.py", line 667, in visit_Assign self.visit(node.value) File "/usr/lib/python2.7/ast.py", line 241, in visit return visitor(node) File "/home/jan/work/projects/MyHDL/myhdl/myhdl/conversion/_toVerilog.py", line 743, in visit_Call self.write(f.__name__) File "/home/jan/work/projects/MyHDL/myhdl/myhdl/_Signal.py", line 479, in __getattr__ return getattr(self._val, attr) AttributeError: 'intbv' object has no attribute '__name__' jan@T60:~/work/projects/MyHDL/SDP_3o4/work$ I did start looking at the MyHDL source, but suspect that this would be a very long route to a solution. My code is only three pages, should I try to convert smaller pieces? Or can anyone else suggest the type of problems/typos I should look for? Jan Coombs -- |