Re: [myhdl-list] Developing PLI module for cosimulation with VCS
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From: Jan D. <ja...@ja...> - 2012-05-11 23:00:45
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On 05/11/2012 03:40 PM, Tom Dillon wrote: > >> I concur, the cver version is more standard (?) should work with most >> Verilog simulators out of the box. If you get the latest development >> code, 0.8dev, there is a modelsim directory in the cosim as well. >> Modelsim had a memory leak some tweaks had to be made and a separate dir >> was made. > > Off topic, but I have been wondering about this. I am using the 0.7 > release. Should I be using the 0.8dev? > > What is new? Do you have to check it out of the repos to use it? In general, I try to make sure that all unit tests work before a development changeset is committed. So your existing code should normally work fine. Of course, new features may be incomplete or not yet work reliably. 0.8 development has stalled somewhat due to circumstances. (When I became active again recently, I intended to "warm up" by first solving some "easy" issues on the newsgroup - a serious misjudgment ;-)). It has modular bit vector types, which I think are a great addition: http://www.myhdl.org/doku.php/meps:mep-106 Some restrictions are not yet checked in the convertor. For a new release I would like to make some progress on Chris Felton's work with what he calls Signal containers, but I still have to start studying the concrete proposals. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |