Re: [myhdl-list] Example of MyHDL for Python Developers Documentation

[Christopher L. <loz...@fr...>]

On 5/11/12 5:13 PM, Christopher Felton wrote:
>     a,b,c,d,w,x,y,z = [Signal(False) for ii in range(8)]
>     iFoo = Foo(a,b,w,x)
>     iBar = Bar(c,d,y,z)
>     toVerilog(iFoo, a,b,w,x)
>     toVerilog(iBar, c,d,y,z)
>
>
>
> In my case, I actually do not want to pass the "ports" to my 
> instantiation but rather the parameters of the design.

Good point.  Let me see if I understood you.  You do have to tell your
hardware modules what signals they are getting.  But passing signals is
not enough. I think when you instantiate a hardware module class you
would want to pass both the ports, and some parameters, such as if you
want a very fast or space efficient implementation of that hardware
module.   Is that a correct understanding?

To do this, all that is needed is that the ports method for the hardware
module class iterates through the instance variables, and only returns
those that are actually a subclass of signals.

I have modified the documentation for the proposed hardware module class
accordingly.

http://wiki.myhdlclass.com:8080/HardwareModuleClass

Existing Class

The other interesting use case is when you are defining a python
HardwareModule class for something that already exists, such as the
embedded multiplier blocks on a FPGA.  There is a need for a python
model of an existing hardware class, one already defined in Verilog.   
Such a class needs to exist in the python model, but does not convert,
because it already exists predefined in Verilog. The instances created
in python, just need to be created in Verilog.   This uses multiple
inheritance, so it can either be used with either a Atomic or Compound
Hardware module. 

Regards
Chris