Re: [myhdl-list] Example of MyHDL for Python Developers Documentation

[Christopher F. <chr...@gm...>]

On 5/3/2012 10:03 AM, G. Andrew Stone wrote:
> In fact, what I thought myHDL was going to let me do is create classes that
> define blocks of logic at the RTL level (synthesizable), perhaps with
> inputs and output "Signals" as variables passed in the constructor and then
> by instantiating those classes I'd be in effect plunking down copies of
> that logic in the FPGA (or within larger logic blocks by instantiating
> these within the constructor of another class).  4 years ago I did not ever
> figure out how to do this... I don't think anything wrapped in a class was
> synthesizable back then.  But maybe that has changed now; I haven't tried
> using classes since.

These are some good points and similar topics pop up here and there. And 
based on these threads Jan D. has made some good changes to the 
documentation; -splitting the sections- and the "What MyHDL is not" 
page.  Hopefully, these help set the expectations and clear up some of 
the confusion?

 From my point of view; your class use case is only partially usable. If 
you pass the ports to the instantiation that object is literally "tied" 
in a particular use.  If I follow your description, in the following 
example I have a hypothetical python class and python function 
implementations, which is which.

    a,b,c,d,w,x,y,z = [Signal(False) for ii in range(8)]
    iFoo = Foo(a,b,w,x)
    iBar = Bar(c,d,y,z)
    toVerilog(iFoo, a,b,w,x)
    toVerilog(iBar, c,d,y,z)

If I added more code (use code not implementation) it might become 
clearer which is which.

In my case, I actually do not want to pass the "ports" to my 
instantiation but rather the parameters of the design.  If we are 
talking about using classes to model and describe complex pieces of 
hardware the "IP" usually includes much more than the hardware description.

If you get a complex piece of IP today is has a ton of stuff that comes 
with it.  It has the hardware description (Verilog/VHDL), scripts galore 
(tcl or worse perl), and models in C/C++/SystemC, Matlab, or whatever 
else HLL.  In my mind, Python/MyHDL objects are a great tool for 
simplifying complex IP organization.

Software to sea of gates (SoG) isn't a MyHDL thing.  This is an industry 
trend / problem to solve.  If you happen to be the person to correctly 
solve, you probably would have you billions and sitting on a beach some 
where :)  That assumes it is solvable with a generic high-level 
description or translation from existing program languages.

<snip>
On 5/3/2012 10:03 AM, G. Andrew Stone wrote:
> The fact of the matter is that Jan seems to have written myHDL to solve
> issues in complex hardware design and hardware simulation that only experts
> in the field can understand (either that or they are such totally obvious
> mistakes in doing a simulation that any software person would think OMG!!
> so we think that that CAN'T be the real issue:-)  ) and a lot of us are
> trying to twist the project to: 1. make it really easy to do quick and
> dirty FPGA hackups 2. learn how to program these "seas of gates".

To get to the quick and dirty FPGA, as Jan D. eluded we probably need a 
large open-source IP collection.  Then someone can tie together a bunch 
of components and implement something.

Regards,
Chris