Re: [myhdl-list] Actel/Microsemi IGLOO nano starter kit

[Norbo <Nor...@gm...>]

Am 10.05.2012, 23:53 Uhr, schrieb Jan Coombs  
<jan...@mu...>:

> On 10/05/12 21:06, Norbo wrote:
>     . . .
>> funny i just completed my UART Design:
>
> Excellent, there's much more to it than mine!  However, it didn't
> survive the fast dispatch and email shredding, so I've attached a
> zipped copy that runs. It has re-joined lines, odd tab chars
> removed, and an edit in the toVHDL line.


There seems to be an indentation error somewhere (i didnt figured out  
where),
it doesnt runs to the end of Simulation
where it prints: "End of Simulation, simulation succesfull!"
fixed also this: ** ToVHDLWarning: Output port is read internally:  
oWrBuffer_full
and removed the tabs.

greetings
Norbo