Re: [myhdl-list] conversion to case statement - odd behaviour?

[Christopher F. <chr...@gm...>]

On 4/30/12 6:12 AM, Jan Coombs wrote:
> In this code the first condition is separated into a separate 'if'
> with the 'elif' lines becoming part of a verilog case statement:
>
>     @always(keyDBclk.posedge)
>     def ledLatchLogic():
>       ''' connect push button event to action '''
>       if   keyEventPB_SW==1:  ledLatch.next = ledLatch>>1
>       elif keyEventPB_SW==2:  ledLatch.next = ~ledLatch
>       elif keyEventPB_SW==4:  ledLatch.next = ~DIP_SW
>       elif keyEventPB_SW==8:  ledLatch.next = (ledLatch<<1)&  255
>       else:                   ledLatch.next = ledLatch
>
> I have tried reversing the order of bit selection, and without the
> 'else'/'default' clause.
>
> Jan Coombs
>
>

I reproduced your post and have encapsulated in a small example (can 
provide if needed).  But what I don't know is if this is bad or not.  Or 
if it is unintended conversion behavior.  It the converted code with the 
mix of if-else and case should synthesize fine (functionally equivalent) 
but I don't know if it is optimal for synthesis or not.

Regards,
Chris