Re: [myhdl-list] When to use @always, @instance and @always_comb

[Jan C. <jan...@mu...>]

On 08/05/12 13:19, Christopher Felton wrote:
> As you mentioned others are trying to give strong opinions on how to
> fish without understanding much about fishing (or why we are fishing).

Whether putting up a TV broadcast aerial, or just building a small 
house we have two principal choices: Understand all the engineering 
implications down to bedrock, or accept a ready made platform.

If the platform is as high as a TV tower, it might be good to know 
something of it's behaviour in wind before climbing up to install 
an aerial, just in case some extra pills are needed!  However, 
looking up at the waving top, and suggesting design modifications 
is likely to lessen the chance of anyone's aerial becoming installed.

> By hinder progress, you simply mean your attention is diverted to a
> lower-level non-related topic?

No, worse than that!  I get very interested in lower levels of the 
design in progress, the stuff that I can't control, and should 
happily entrust to synthesis tools.

> In general the claim to fame by [1] is
> that it takes the known, successful, design techniques and does the
> translation to async itself.

We might never need anything better!:)  Since RTL balances delays 
between latches (to a first approximation), then replacing buffers 
with 'signal re-synchronisation' logic should just work.

However, I dislike black boxes, so shall insist that I need to know 
the details, so that I can predict any odd cases where simple 
translation is not the best option.

> MyHDL should be as useful as any other tool for [1].
Yes, I'm just starting to appreciate it's power.  I struggle to 
read verilog in places where it is very terse, but also soon tired 
of using VHDL where so many things have to be written in triplicate.

> Feedback is always welcome, it might be challenged but I believe you and
> most have found that the group here is fair.

Yes, it's been a largely pleasant experience, and I feel 
sufficiently supported.

> It looks like you have been successful with MyHDL.  ...
The UART was the first sign of reasonable productivity. 
Translating the processor designs from verilog to MyHDL was an 
up-hill struggle - two unfamiliar languages, and no obvious means 
of testing anything less that a working whole.

Thanks for the encouragement, Jan Coombs.
-- 
[1] www.achronix.com