Re: [myhdl-list] Restrictions for conversion

[Christopher F. <chr...@gm...>]

>
>> This might be the path of least resistance right now.  But I don't think
>> there is a reason that the converted couldn't generate
>>
>>        reg [7:0] out1 = 8'd0;
>>        reg [7:0] aListSig [0:10-1];
>>        // initial blocks ...
>>        @always_comb begin
>
> nice: @always_comb begin a myhdl artefact ;)
>
>>            aListSig[3] = in_data
>>            out1 = aListSig[3]
>>        end
>>

Yes, typo should not have included the '@'.  Note: *always_comb* and 
*always_ff* are new key words in later version of Verilog and support by 
most Sysnthesis tools, even the free ones.  Or it is fine to use always 
@(*) or explicitly include the sensitivity list as the VHDL conversion does.

Regards,
Chris