Re: [myhdl-list] Example of MyHDL for Python Developers Documentation

[Jan D. <ja...@ja...>]

On 05/03/2012 10:23 PM, G. Andrew Stone wrote:
> Hi Jan,
>
> Let me try to say it in another way.  Please forgive any
> inaccuracies; its been a few years! :-)
>
> If my synthesizable hardware description was put in a simulation
> black box (call it "hdl") with some simple API that could be used
> like:
>
> hdl.start() for time in range(1,whatever): output_signals =
> hdl.next(list_of_input_signals)
>
> then as a software engineer I'd completely understand how to write a
> complex simulation and testbench around it.  For example, if my "hdl"
> object defined a PCI bus card I could pretty easily write Python code
> that jams in a bunch of fake PCI requests and make sure the right
> stuff comes out.  I could easily make up code that runs a bunch of
> these black boxes simultaneously and use unsynthesizable python to
> "glue" them together to make a larger system -- thereby simulating a
> subset of some larger system.  I could even have each black box
> "running" at different clock speeds.  Or I could even hook the
> simulation black box up to the actual code that will run on a CPU and
> talk to my FPGA.
>
> So I (as a software professional) don't need myHDL to help me do
> that.  What I need is it to help me with is what's inside that black
> box.  But the docs (but please remember my heavy use was several
> years ago) keep trying to teach me how to do the testbench part.
> This confused me because I kept thinking I was writing synthesizable
> code.

I don't want to start a discussion about the merits of your point
of view, but again I point out that heavy MyHDL users, myself included,
see things entirely differently.

I developed MyHDL because I wanted to do modeling and verification
in python, and stock python didn't give me the fine-grained threading
and event-driven paradigm needed. At that time, it was not clear if
it was desirable or even possible to do conversion as a path to synthesis.

If synthesizable code would be all it did, I wouldn't see the point.
I always assumed that would be obvious to other MyHDL users but
I recognize this is an assumption that may have been too implicit.

Anyway, it explains why I'm not interested in discussions when MyHDL
is limited to that aspect: it is not my world. And there are further
reasons. The continuous identification of MyHDL "limitations" with
conversion or even synthesis limitations is tiresome. And it is
demotivating. I hardly hear any talk about the HDL limitations
that MyHDL actually lifted in comparision to $$$ synthesis, e.g.
by the way conversion works after elaboration, and how it does
integers.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com