Re: [myhdl-list] How to make MyHDL Object-Oriented

[Jan D. <ja...@ja...>]

On 05/04/2012 02:18 PM, Christopher Lozinski wrote:
> On 5/4/12 5:04 AM, Jan Decaluwe wrote:
>> On 05/04/2012 01:45 AM, Christopher Lozinski wrote:
>>> Thanks enormously to Andy Stone for pointing out that MyHDL,
>>> while in Python is not object-oriented.  There is no hardware
>>> module class, just a generator, and decorator which are
>>> functional approaches.
>> How can you even say this,
>
> Actually the wiki says it.
>
> http://www.myhdl.org/doc/0.6/manual/intro.html In MyHDL, classic
> functions are used to model hardware modules. In particular, the
> parameter list is used to define the interface.

Point taken. However, I am not sure how to change that for full
generality in an introductory chapter, without being overly confusing
to new users.

However: it is true that I think that the approach based on functions
is the best choice for a first step. It is correct that I wanted to make
things as simple as possible for hardware designers, especially Verilog
designers, with no exposure to object-orientation in their HDLs.
It is also true that conversion was written with this choice in mind
in the first place.

> I would rather see objects being used to model hardware modules. In
> particular the instance variables should be used to model the
> interface. (and internal signals).

You can do that today.

> Here is another one.
> http://www.myhdl.org/doc/current/manual/modeling.html
>
> In MyHDL, an instance is recursively defined as being either a
> sequence of instances, or a generator. Hierarchy is modeled by
> defining instances in a higher-level function, and returning them.
>
> That does sound to me like a functional approach. I would rather see
> hardware modules defined "in a higher level object" a module with
> parent and child nodes. I would expect a hierarchy of chip modules,
> each of which points to its children and parents.
>
> Then let me quote others: Andrew Stone said this is what he
> expected:
>
> In fact, what I thought myHDL was going to let me do is create
> classes that define blocks of logic at the RTL level (synthesizable),
> perhaps with inputs and output "Signals" as variables passed in the
> constructor and then by instantiating those classes I'd be in effect
> plunking down copies of that logic in the FPGA (or within larger
> logic blocks by instantiating these within the constructor of another
> class). 4 years ago I did not ever figure out how to do this... I
> don't think anything wrapped in a class was synthesizable back then.
> But maybe that has changed now; I haven't tried using classes since.
>
> And yes, Dillon wrote that he does this, but I think we will find the
> details of how he does it are different than at least what I would
> expect. In particular MyHDL does not pass variables into the object
> constructor, it passes them into the generator. There are no parent
> or child links.
>
>
>> when the manual has a section about object-oriented modeling, which
>> has a Queue class, which you have just been struggling with?
>
> If I recall correctly, the Queue class is not inside a @always,
> @instance, or @always_comb, so it is not synthesizable. While MyHDL
> is quite general, it is only the synthesizable stuff I am interested
> in.

Then you should clearly say so in your communication. Otherwise your
statements are totally confusing to people, including myself, who
are equally interested, or even more so, in other aspects of MyHDL.

> Jan Decaluwe wrote:
>
>> Perhaps this stuff really is too hard for the "general python
>> developer", though I
>
>> still don't understand why.
>
> Because it does not fit the way we see the world. Different people
> have different world views. I am doing my best to explain my world
> view. In particular one of my concepts is that every real world thing
> should be represented by a class. So flip flops, adders, multipliers
> should each be represented by a class. And then I mostly want the
> documentation to be a listing of the classes, representing physical
> objects, available to me to work with. And yes the existing MyHDL
> documentation would also be useful.

But that is a low-level view that I'm not interested in at all!
I don't care about models for flip-flops, adders, multipliers etc -
I have synthesis tools that infer them efficiently and by the dozen
from the behavior of my code, without requiring my attention.
(Of course, I know about them very well, to judge the quality
of the synthesis result in the back end).

But if you insist - you can do that today, and then work at
the net list level in MyHDL connecting them. Just add some print method
to each class that prints out the instance representation in some
technology in Verilog and you are done - you have a netlist
generator. No conversion needed, and no synthesis for that matter.

> I now understand it is a hugely different view from the prevailing
> view on this mailing list. And that is why we keep clashing. It is
> why I am just not able to 'get' MyHDL. Because we are operating under
> two different world views.

And I don't buy that. More important than the software
technique is the abstraction level at which
you are working. Your object-oriented approach is just a low-level
approach in disguise - not interested.

You don't get MyHDL because you don't yet get the basics of
HDL-based design. Unfortunately, I don't see an alternative
of getting your hands dirty and building up experience
yourself, painstakingly.

Trying out Verilog, as you announced, may actually be a wise
step. If you are happy with it, all the better. But if you
are not, I trust the discussion will become much easier.

Look at it this way. Synopsys has become very rich by selling
great synthesis tools. But after all these years, I am still
not aware of a reference work that I can recommend to really
learn what synthesis can do.

Don't expect some poor open-source guys to fill in that gap.

>
> -- Regards Christopher Lozinski
>
> Check out my iPhone apps TextFaster and EmailFaster
> http://textfaster.com
>
> Expect a paradigm shift. http://MyHDL.org
>
>
>
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
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