Re: [myhdl-list] Example of MyHDL for Python Developers Documentation
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jandecaluwe
From: Jan D. <ja...@ja...> - 2012-05-03 20:50:47
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On 05/03/2012 10:23 PM, G. Andrew Stone wrote: > Hi Jan, > > Let me try to say it in another way. Please forgive any > inaccuracies; its been a few years! :-) > > If my synthesizable hardware description was put in a simulation > black box (call it "hdl") with some simple API that could be used > like: > > hdl.start() for time in range(1,whatever): output_signals = > hdl.next(list_of_input_signals) > > then as a software engineer I'd completely understand how to write a > complex simulation and testbench around it. For example, if my "hdl" > object defined a PCI bus card I could pretty easily write Python code > that jams in a bunch of fake PCI requests and make sure the right > stuff comes out. I could easily make up code that runs a bunch of > these black boxes simultaneously and use unsynthesizable python to > "glue" them together to make a larger system -- thereby simulating a > subset of some larger system. I could even have each black box > "running" at different clock speeds. Or I could even hook the > simulation black box up to the actual code that will run on a CPU and > talk to my FPGA. I hear what you say - but would this not mean that you had to write an ad-hoc event-driven system, similar to what MyHDL provides out of the box? -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |