Re: [myhdl-list] Example of MyHDL for Python Developers Documentation
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Re: [myhdl-list] Example of MyHDL for Python Developers Documentation
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From: Jan D. <ja...@ja...> - 2012-05-03 20:01:50
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On 05/03/2012 05:03 PM, G. Andrew Stone wrote: > I taught myself RTL using myHDL a long time ago and then learned Verilog by looking at what it output and modifying it. I'm still a beginner with it though... I mean its not my job so I haven't done much more then what people would do in college courses -- small stuff like PWM LEDs, drive stepper motors, etc. > > But folks, I think that Christopher has a few good points. It was HARD to learn it (but easier then learning straight Verilog). The biggest issue was figuring out what can be synthesized or not. I mean, from a SW developer's perspective, I know perfectly well how to write a simulation at multiple abstraction levels. In fact the whole "yield" thing forces the simulation into a certain "style" which can be limiting. In essence, as a software professional, I don't need myHDL to help me write them at multiple abstraction levels EXCEPT for the lowest -- i.e. a synthesizable simulation. But -- no offense intended -- judging by the TCL (and C) code I've seen I can certain see how hardware guys might really need it!!! :-) > > In this example: http://www.myhdl.org/doc/current/manual/modeling.html#object-oriented-modeling its still unclear whether the "queue" class was synthesizable or not (just by reading the docs, I mean you could try it!). But it would be really nice if the document clearly marked what is expected to be synthesizable. Frankly it would be awesome if unsynthesizable stuff was magically highlighted in red in my emacs editor but I don't think that will happen soon :-). > > In fact, what I thought myHDL was going to let me do is create classes that define blocks of logic at the RTL level (synthesizable), perhaps with inputs and output "Signals" as variables passed in the constructor and then by instantiating those classes I'd be in effect plunking down copies of that logic in the FPGA (or within larger logic blocks by instantiating these within the constructor of another class). 4 years ago I did not ever figure out how to do this... I don't think anything wrapped in a class was synthesizable back then. But maybe that has changed now; I haven't tried using classes since. > > Some comments inline: > > > On Thu, May 3, 2012 at 9:35 AM, Christopher Lozinski <loz...@fr... <mailto:loz...@fr...>> wrote: > > So here is an example of the what I think python developers would like > to see. > > http://wiki.myhdlclass.com:8080/Documentation > > The embedded Decorator link is an excellent resource. I make the clock > cycle on Delay(1) not 20. I try to describe the digital design issues > for consumption by a python developer. > > As for the other discussions, I am not quite sure why I generate so much > negative response. I really liked David's comment. > > On 5/3/12 6:16 AM, David Arnold wrote: > > My view of gratis software is that I'm grateful for what's given and the creator(s) are under no obligation to do anything. > My mistake. It is easy to think of MyHDL as a shared project with > people having shared direction. And then we get to discuss the shared > direction. The reality is that each person does whatever they want. > Thank you for clearing up my understanding of open source projects. > > > Christopher, it sounds like you are being sarcastic here but if so in fact you really are mistaken about what happens in open source projects with no paid engineers. The purpose of discussion is only to give a person ideas. That person will then go off and do whatever they want. And whether that gets back into the main tree is entirely up to the owners of the project, who will do whatever they want with the submission :-). If they don't take it you may get a fork... > > The fact of the matter is that Jan seems to have written myHDL to solve issues in complex hardware design and hardware simulation that only experts in the field can understand (either that or they are such totally obvious mistakes in doing a simulation that any software person would think OMG!! so we think that that CAN'T be the real issue :-) ) and a lot of us are trying to twist the project to: 1. make it really easy to do quick and dirty FPGA hackups 2. learn how to program these "seas of gates". > > > Nor am I asking for the senior MyHDL developers to be writing this. > Writing up documentation is a great way to learn the systems. But if > they would be so kind as to proofread it that would be a huge help. > > > Then write it... but honestly WRT proofreading I have one comment. From reading this list it seems like you keep claiming the X does not exist and then Jan has to go off and point to the spot in the docs. So the law clerk is having the lawyer run around and look stuff up... don't be a help vampire: http://slash7.com/2006/12/22/vampires/ > > Cheers! > Andrew > > > > ------------------------------------------------------------------------------ > Live Security Virtual Conference > Exclusive live event will cover all the ways today's security and > threat landscape has changed and how IT managers can respond. Discussions > will include endpoint security, mobile security and the latest in malware > threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ > > > > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |
