Re: [myhdl-list] Example of MyHDL for Python Developers Documentation

[Jan D. <ja...@ja...>]

On 05/03/2012 05:03 PM, G. Andrew Stone wrote:
> I taught myself RTL using myHDL a long time ago and then learned
> Verilog by looking at what it output and modifying it.  I'm still a
> beginner with it though... I mean its not my job so I haven't done
> much more then what people would do in college courses -- small stuff
> like PWM LEDs, drive stepper motors, etc.
>
> But folks, I think that Christopher has a few good points.  It was
> HARD to learn it (but easier then learning straight Verilog).

Thanks for that comment - it means that I reached my goal your case:
it is hard work, yes (see "Why MyHDL"), but as long as it's easier
than straight Verilog (and free),one gains.

> The biggest issue was figuring out what can be synthesized or not.  I
> mean, from a SW developer's perspective, I know perfectly well how to
> write a simulation at multiple abstraction levels.  In fact the whole
> "yield" thing forces the simulation into a certain "style" which can
> be limiting.  In essence, as a software professional, I don't need
> myHDL to help me write them at multiple abstraction levels EXCEPT for
> the lowest -- i.e. a synthesizable simulation.

I don't understand that. If I want to verify a synthesizable RTL
description, which is a special kind of an event-driven model, I
need event-driven models and test benches as a verification
environment. So I really need event-driven and high-level modeling
combined - something MyHDL gives me and stock Python does not.

Note also that your comment is the opposite of what Uri Nix just
said in another post.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com