Re: [myhdl-list] When to use @always, @instance and @always_comb

[Jan D. <ja...@ja...>]

On 05/03/2012 02:30 AM, David Greenberg wrote:
> The problem is that all of the references are in Verilog and VHDL. If
> you want to start using MyHDL now, you first have to learn Verilog,
> then you can start using MyHDL. This is different than how software
> languages have progressed, in that you don't, i.e. need to know C to
> learn Ruby.

Personally, I don't think there's a good reference that teaches
HDL-based design. If you have one, let me know.

The books I know tend to teach how to describe FFs, gates,
adders, Moore, Mealy etc in Verilog/VHDL - something no one
really does (I hope) because we use synthesis for that. Then
there is an appendix about synthesis instead making it an integral
part of the material.

Actually I think the section about RTL in MyHDL is not that
bad - it teaches the templates that we all use for synthesizable
logic, and includes material about FSM design, which I think is
the basic building block in RTL design.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com