Re: [myhdl-list] When to use @always, @instance and @always_comb

[Christopher L. <loz...@fr...>]

On 5/2/12 9:18 PM, Tom Dillon wrote:
> OK, but do you expect the MyHDL documentation to teach you basics of
> digital design? 
No not really.  But I do want a clear set of digital designs, presented
one at a time in the docs. Each one describing a new MyHDL concept.  
Here is the index for the section on modelling.

  * Modeling techniques
    <http://www.myhdl.org/doc/current/manual/modeling.html#>
      o Structural modeling
        <http://www.myhdl.org/doc/current/manual/modeling.html#structural-modeling>

          + Conditional instantiation
            <http://www.myhdl.org/doc/current/manual/modeling.html#conditional-instantiation>
          + Lists of instances and signals
            <http://www.myhdl.org/doc/current/manual/modeling.html#lists-of-instances-and-signals>
          + Converting between lists of signals and bit vectors
            <http://www.myhdl.org/doc/current/manual/modeling.html#converting-between-lists-of-signals-and-bit-vectors>
          + Inferring the list of instances
            <http://www.myhdl.org/doc/current/manual/modeling.html#inferring-the-list-of-instances>
      o RTL modeling
        <http://www.myhdl.org/doc/current/manual/modeling.html#rtl-modeling>

          + Combinatorial logic
            <http://www.myhdl.org/doc/current/manual/modeling.html#combinatorial-logic>

              # Template
                <http://www.myhdl.org/doc/current/manual/modeling.html#template>
              # Example
                <http://www.myhdl.org/doc/current/manual/modeling.html#example>
          + Sequential logic
            <http://www.myhdl.org/doc/current/manual/modeling.html#sequential-logic>

              # Template
                <http://www.myhdl.org/doc/current/manual/modeling.html#model-seq-templ>
              # Example
                <http://www.myhdl.org/doc/current/manual/modeling.html#model-seq-ex>
          + Finite State Machine modeling
            <http://www.myhdl.org/doc/current/manual/modeling.html#finite-state-machine-modeling>
      o High level modeling
        <http://www.myhdl.org/doc/current/manual/modeling.html#high-level-modeling>

          + Modeling with bus-functional procedures
            <http://www.myhdl.org/doc/current/manual/modeling.html#modeling-with-bus-functional-procedures>
          + Modeling memories with built-in types
            <http://www.myhdl.org/doc/current/manual/modeling.html#modeling-memories-with-built-in-types>
          + Modeling errors using exceptions
            <http://www.myhdl.org/doc/current/manual/modeling.html#modeling-errors-using-exceptions>
          + Object oriented modeling
            <http://www.myhdl.org/doc/current/manual/modeling.html#object-oriented-modeling>


This is all really about Python and MyHDL.  Nothing about chips.  Not
that much about computational models of circuits.  And in particular,
not at all clear where chip modeling ends and other modeling begins. 
Nor what kind of chips use  @always, @instance and @always_comb. The
focus is not on the models of digital circuits, it is on the features of
MyHDL.

How about structuring it like:
   Flip Flop
   Signal
   Clock
   Wires
   Ram Model
   Rom Model
   Fixed Point
   Sequential Logic
   Finite State Machine
   Bus.
   Etc.

Then each chip section could describe one of the features of MyHDL.  I
am sure the hardware guys can think of a hardware example that
illustrates each of the above concepts. 

Actually this approach has the real nice property, that you are
effectively documenting the existing components.  Right now things are
scattered, it took me a while to find the memory models and the fixed
point models.  I did not realize they existed.   And more importantly
you are publishing a series of digital circuit models.  The software
developers can figure out the MyHDL commands.  The digital circuit
models is where they need the help. 



-- 
Regards
Christopher Lozinski

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