Re: [myhdl-list] When to use @always, @instance and @always_comb

[Christopher F. <chr...@gm...>]

On 5/2/12 7:30 PM, David Greenberg wrote:
> The problem is that all of the references are in Verilog and VHDL. If
> you want to start using MyHDL now, you first have to learn Verilog,
> then you can start using MyHDL. This is different than how software
> languages have progressed, in that you don't, i.e. need to know C to
> learn Ruby.
>

But a manual for the Ruby language will expect that you know how to 
program something, how to use a computer, etc.  It doesn't start from 
step one (what is step one?).

I do agree, there are different users that would be interested in MyHDL. 
  Those who know programming and basic hardware so the references to 
Verilog/VHDL could be bewildering.  On the flip-side those who are 
experienced/familiar with Verilog/VHDL the direct path would be to 
explaining MyHDL is to compare/contrast to Verilog/VHDL.

Although, the manual does mention Verilog and VHDL I think it does a 
good job of explaining the concepts, such that a user would not need to 
know Verilog/VHDL.  The _background_ section suggests knowing 
Verilog/VHDL is helpful but not required.  As mentioned you want a 
direct path for those that know HDLs without excluding programmers.  I 
think the manual does a decent job finding that balance.

Maybe a "read first", one for programmers and one for HDLers.  Or 
separate overview(s) could be useful?  But I don't think it is 
reasonable to expect the MyHDL manual to include logic circuits 101. 
That is out of the context of the manual.

Regards,
Chris