Re: [myhdl-list] When to use @always, @instance and @always_comb

[Christopher F. <chr...@gm...>]

On 5/2/2012 1:52 PM, Uri Nix wrote:
> IMHO it /is/ confusing, since the previous topics in the chapter are
> synthesis oriented.

The manual under "Modeling techniques" currently progresses; structural, 
RTL, High-level.  Do you think a top-down versus bottom-up order would 
be better?  Someone *without* a HW design background may find; 
High-level, RTL, structural order less confusing?  Or, in your opinion, 
do you think it needs to be a completely separate chapter?

Regards,
Chris

>
> I have had very good experience with MyHDL for system modelling, which uses
> a different mindset than the FPGA direction. It is amazingly powerful,
> follows similar idioms as in SystemC with the ease of Python, and might use
> some more mention.
>
> Cheers,
> Uri
>
>
> On 2 May 2012 18:55, Tom Dillon<td...@di...>  wrote:
>
>>   I think the manual is clear and it makes pretty good sense what can be
>> converted.
>>
>> One of the great things about MyHDL/Python is that as long as your code at
>> the lowest level is RTL, then it will convert.
>>
>> You can use all the power of Python of top of that to make very high level
>> structures.
>>
>>
>>
>> On 05/02/2012 10:30 AM, Jan Decaluwe wrote:
>>
>> On 04/27/2012 02:52 AM, Christopher Lozinski wrote:
>>
>>
>>   The higher level approach is to model things as objects. There is a
>> queue example in the docs.  This stuff blows my mind.  How that can be
>> synthesized, what it means in terms of hardware functions, I really do
>> not yet understand.   Sure the queue example is easily understandable to
>> a software engineer, but what does that look like when converted?
>>
>>   I went back to the manual, to understand where so much confusion can
>> come from.
>>
>> But really, I don't see it. I think the manual is crystal clear. In the
>> chapter you refer to, it describes a number of modeling options that
>> MyHDL supports. When it talks about RTL, it explicitly makes the connection
>> with synthesis. Then it moves on to high-level modeling - I think
>> it's obvious that there is no direct link with synthesis.
>>
>> To understand the link between conversion and synthesis, move to the
>> chapter about conversion. It explicitly states that the first goal
>> of conversion is synthesis, but also that the convertible subset
>> is more general than the synthesizable subset. And it describes
>> the convertible *subset*.
>>
>>
>>
>>
>> ------------------------------------------------------------------------------
>> Live Security Virtual Conference
>> Exclusive live event will cover all the ways today's security and
>> threat landscape has changed and how IT managers can respond. Discussions
>> will include endpoint security, mobile security and the latest in malware
>> threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>>
>
>
>
> ------------------------------------------------------------------------------
> Live Security Virtual Conference
> Exclusive live event will cover all the ways today's security and
> threat landscape has changed and how IT managers can respond. Discussions
> will include endpoint security, mobile security and the latest in malware
> threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/
>
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list