[myhdl-list] conversion to case statement - odd behaviour?

[Jan C. <jan...@mu...>]

In this code the first condition is separated into a separate 'if' 
with the 'elif' lines becoming part of a verilog case statement:

   @always(keyDBclk.posedge)
   def ledLatchLogic():
     ''' connect push button event to action '''
     if   keyEventPB_SW==1:  ledLatch.next = ledLatch>>1
     elif keyEventPB_SW==2:  ledLatch.next = ~ledLatch
     elif keyEventPB_SW==4:  ledLatch.next = ~DIP_SW
     elif keyEventPB_SW==8:  ledLatch.next = (ledLatch<<1) & 255
     else:                   ledLatch.next = ledLatch

I have tried reversing the order of bit selection, and without the 
'else'/'default' clause.

Jan Coombs