Re: [myhdl-list] Restrictions for conversion (initial values)

[Christopher F. <chr...@gm...>]

On 4/25/12 8:30 AM, Norbo wrote:
>
>>> The initial values for the array signal are enough for a synthesizable
>>> approach.
>>> The Function with is used in the VHDL code is just another way which can
>>> be used to give the
>>> signals in the array there initial values in a more procedural way (for
>>> vhdl). If you have the procedure
>>> wich gives the values in python, you can write the initial values in
>>> vhdl
>>> to the array directly.
>
>> Is this true for Verilog and VHDL?  And is it true across multiple
>> vendor tools?  IMO the actual creation of the pre-init RAM is less
>> important, unless widely advertised, than wide support of pre-init.
>> Reworded, adding the init support even if it doesn't support pre-init
>> RAM in the vendor synthesis is ok, IMO.
> ......
> ......
>> But to clarify, you do not see initial value errors with Verilog in
>> Quartus?
>
> I looked at it more closely now, and here is what i found :
> Bassicaly a signal array with initial value can be used, meaningfull in
> the following scenarios:
>
> 1. reading it from a combinatorical process
> 	->   vhdl synthesis works&   verilog syntesis works (but signal array
> must be defined as "reg")
>
> 2. reading it synchron (clocked)
> 	->  vhdl synthesis works&   verilog syntesis works (but signal array must
> be defined as "reg")
>
> 3. reading it synchron (clocked) and writing it synchron
> 	->  vhdl synthesis works&   verilog synthesis works (signal array is
> allready defined as "reg")
>
> 4. reading it synchron (clocked) and writing it in a combinatorical process
> 	->  vhdl synthesis works&   verilog synthesis doesnt work !!! (because
> signal cant be defined as reg when you write to in a combinatorical
> process. So if you write to just one signal in the array the whole array
> needs to be defined as wire and you cant use the
> initial statment for that signal array, so you cant initialize all the
> other signals which are not written in a combinatorical process.
> it normally makes sense that  if you have a inital value in a signal that
> you are not allowed to overwrite it immidiatly with an combinatorical
> assignment.
> But the problem is that if you just use one signal of the array to write
> to it in a combinatorical process, you "lose" the hole array.
>
> Addition: "if there is a asynchron reset in a clocked process where you
> assign on of the array signals a reset value, then the verilog synthesis
> works with the initialized array"

This is an alternative to the initial block initial values (pre-init RAM)?

>
> 5. reading and writing in a combinatorical process
> same problem in verilog ->  you cant have the signal array be defined as
> "wire" and use the init block statment in verilog.
> Or in other words: If the signal array is defined as "reg" you cannot
> write to it in a combinatorical process.
>
In the above can you clarify between what synthesizes and what creates 
RAM/ROM as expected.  As we discovered with Quartus, it will not use a 
BRAM for a ROM when an always_comb is used to describe a ROM, the ROM 
needs to be clocked.  But this does not seem to be the case for the 
Xilinx tools.  One case is that is synthesizes and no BRAM used the 
other is synthesizes and BRAM used.

We might want to create a wiki page with a table and summarize these 
results.  The question would be where on the wiki, as a simple project 
page, a RAM/ROM cookbook page, or an FAQ page?

Regards,
Chris