Re: [myhdl-list] Floating Point MEP

[Christopher L. <loz...@fr...>]

On 4/25/12 4:06 PM, Jan Decaluwe wrote:

>
>     Note however that in contrast to what you suggest, it is
>     perfectly possible to *simulate* "hierarchical" signals.
>     Simulation is intended to be completely general.

Great to know!

    The basic problem as I see it remains that the convertor
    (or "exporter" as you call it) is a tool which is
    'event-accurate'. It cannot "export" a combinatorial
    operator such as '*' to a module that has pipelining.
    The operator operates within a clock cycle, the module
    needs several.

Understood.  I was not planning on converting the innards of the
floating point module. It is not "in the convertible subset".   I just
wanted something that I could simulate and that would also run in
Verilog.   I will use a floating point multiplication library in
Verilog.    Not quite sure how I am going to do the conversion.  I
expect that I will write some "user defined verilog or vhdl" code.

Anyhow MyHDL does need the floating point modules.  If I get them up and
simulating correctly, then I am sure other newbies will start using
them.   Even without the conversion stuff.  Anyone interested?   

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org