Re: [myhdl-list] Floating Point MEP

[Jan D. <ja...@ja...>]

On 04/24/2012 12:53 PM, Christopher Lozinski wrote:
> Here is a MEP for floating point numbers.
>
> http://wiki.myhdlclass.com:8080/FloatingPoint
>
> The basic idea is to create a new signal type, float, out of sign,
> mantissa and exponent signals. In MyHDL model the calculation using
> python floating point operators with the appropriate delay. When
> exporting it call an existing Verilog or VHDL library. The big change
> is that MyHDL would need to understand hierarchical signals. Maybe it
> is not that hard. When dealing with a signal in a sensitivity list,
> MyHDL would first check it it were hierarchical, if it were, MyHDL
> would add all of the sub signals to the sensitivity list. And from
> there MyHDL could continue operating as before.
>
> If you are interested, I invite you to read the details in the MEP.
>
> http://wiki.myhdlclass.com:8080/FloatingPoint

I have a hard time understanding exactly what you expect.
(btw this post is buried deep in a thread where it doesn't belong.)

As you mentioned, all of this has been discussed before, I don't
see new elements.

The basic problem as I see it remains that the convertor
(or "exporter" as you call it) is a tool which is
'event-accurate'. It cannot "export" a combinatorial
operator such as '*' to a module that has pipelining.
The operator operates within a clock cycle, the module
needs several.

Note however that in contrast to what you suggest, it is
perfectly possible to *simulate* "hierarchical" signals.
Simulation is intended to be completely general.

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
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