Re: [myhdl-list] MyHDL timescale

[Jan D. <ja...@ja...>]

On 04/19/2012 08:55 AM, Thomas Heller wrote:
> MyHDL uses 'steps' as time unit.  When it writes VCD files with
> traceSignals, one time unit is defined as 1ns.
>
> Considering the speed of todays logic, this is very coarse.
>
> I would find it convenient to be able to specify sub-nanosecond
> delays as floats,

Mm, simulation is based on discrete time steps so there
must be some smallest unit defined.

What Verilog does is to define the physical meaning of
the unit step with a global directive, but I'm not sure
even this is useful for MyHDL (accurate gate level timing
level simulations are not its target application). Within
a MyHDL simulation, you can attach any phyical meaning
that you want to the unit step.

> and to make the timescale written into the
> vcd files configurable.

Agreed - I have gone ahead and implemented a 'timescale'
directive as an attribute of the traceSignals function.
Actually, this existed for toVerilog also but was not
yet documented.

I have implemented this in the 0.8-dev branch. I have also
updated the documentation immediately. In the future, I
will try to keep a development version of the documentation
up to date and on-line, instead of doing it all at release
time. I have added the link to it in the Development Zone on the
web site.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com