Re: [myhdl-list] Floating Point MEP

[Christopher L. <loz...@fr...>]

On 4/24/12 8:40 AM, Tom Dillon wrote:
> My other 2 cents is, for something as complex as a floating point
> operator, say multiply I don't think you would have much luck
> overriding the operator as in:
>
> c = a * b
>
> I think you really want a module instantiation, since you want to be
> able to pass parameters along with the signals. Such as number of
> pipelines, type of rounding and so on. That would lead to a much more
> worth while library component. 
Agreed.  Sorry if my posting was not clear.  I have edited the wiki, it
now says. 


    Implementing Floating Point Multiply

Conceptually, given a binary sign, an intbv exponent, and a fixed point
mantissa, it is not that hard to implement a floating point multiply.

http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/BinMath/multFloat.html

But, that does look like a lot of work. And it is complex to figure out
the pipelining.

So my plan is to create MyHDL modules for floating point multiplication,
division and addition/subtraction. Each such module will accept inputs
of two floating point signals. Internally it will convert the signals
into a python floating point number, and then in MyHDL simulation it
will just use python floating point multiplication.

  * output = input1 * input2

Then the output signals will be set using the results from the python
computation.

Of course this will not work on export, so on export there will be a
call to a Verilog library to do the hard work.

And then pipelining also has to be represented.  And delays have to be
added.

Is that better? 

That page now also has the creative commons license.

-- 
Regards
Christopher Lozinski

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