[myhdl-list] Floating Point MEP

[Christopher L. <loz...@fr...>]

Here is a MEP for floating point numbers.

http://wiki.myhdlclass.com:8080/FloatingPoint

The basic idea is to create a new signal type, float, out of sign,
mantissa and exponent signals. In MyHDL model the calculation using
python floating point operators with the appropriate delay. When
exporting it call an existing Verilog or VHDL library. The big change is
that MyHDL would need to understand hierarchical signals. Maybe it is
not that hard. When dealing with a signal in a sensitivity list, MyHDL
would first check it it were hierarchical, if it were, MyHDL would add
all of the sub signals to the sensitivity list. And from there MyHDL
could continue operating as before.

If you are interested, I invite you to read the details in the MEP.

http://wiki.myhdlclass.com:8080/FloatingPoint

-- 
Regards
Christopher Lozinski

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Expect a paradigm shift.
http://MyHDL.org