Re: [myhdl-list] Restrictions for conversion

[Christopher F. <chr...@gm...>]

>
>
> Of curse this doesnt get mapped into ram, but the code is synthesisable
> and the netlist-viewer seems to show
> a good result.
> In the patch i posted previously i noticed an error i made:
> The verilog code is not synthesisable if the list of signals is only
> used in reading, because then the toVerilog conversion
> defines the list of signals with the "wire" keyword ( in the case above
> "wire [7:0] aListSig [0:10-1];" )
> but it is not possible to use the "initial block" with the wire keyword.
> so i changed it in this case to "reg" (in the case above "reg [7:0]
> aListSig [0:10-1];")
> I just appended the new patch.
>
>
>
> greetings
>
> Norbo
>
>

I was taking a look at your patch, your patch is not based on the latest 
0.8-dev branch.  There are enough changes that it doesn't auto import to 
the 0.8-dev branch.

I don't know if the _doinit flag is actually needed?  I believe the 
conversion code can determine if the value should be written or not 
without modifying the Signal or intbv objects.  As your modified intbv 
does, it can always create the initial value unless the Signal/intbv 
init value is None.

Lastly, the changes do break the unit-tests.  As mentioned, the patch 
didn't auto import.  I believe I got all the changes manually but 
possibly something was missed in the manual addition of the changes.  I 
think removing the _doinit will fix the failures (but I didn't really 
look that closely).

Regards,
Chris