Re: [myhdl-list] What MyHDL is not

[Christopher F. <chr...@gm...>]

On 4/23/12 5:23 AM, Jan Decaluwe wrote:
> I have written a page describing what MyHDL is not:
>
> http://www.myhdl.org/doku.php/whatitisnot
>
I believe this will help inform new users.  We often get new users, I 
believe, with unrealistic expectations of MyHDL.

Some comments, cross linking to the "Why MyHDL" page (and vise-versa) 
could be useful.  We want to be useful setting expectations but also 
want to *highlight* the benefits :)

In the _It is not well suited for gate level simulation_ section.  You 
might want to mention co-simulation.  A potential user might come away 
with the wrong impression that they will need to redo a fair amount of 
verification implementation in Verilog/VHDL.  Rather, they should use a 
Verilog/VHDL simulator in conjunction to verify structural-physical 
correctness.

Regards,
Chris