Re: [myhdl-list] Why MyHDL (New MyHDL Wiki)

[Jan D. <ja...@ja...>]

On 04/22/2012 01:21 PM, Christopher Lozinski wrote:
> First thank you for your excellent email two days ago, and even more so
> for what you wrote this morning.
>
> On 4/22/12 5:25 AM, Jan Decaluwe wrote:
>> I
>> believe the main problem in HDL-based design is verification, and
>> how MyHDL (unlike Migen) helps you by the fact that you
>> can use the same modelling paradigm for high-level models and
>> test benches as for synthesizable logic.
>>
>> You seemed surprized, which I found suprizing in turn. Is
>> it so different in software? Really, getting those gates into
>> an FPGA is the easy part. The difficult part is getting
>> them to work properly.
>>
>>
>> Well, I don't. Verification is the problem. The reason why I
>> think the abstraction level of synthesizable logic should
>> be as high as possible, is because that leaves more time
>> for verification.
>
> I think this is the central point from a marketing perspective.  And
> once you believe this, then the advantage of MyHDL is clear.  Only MyHDL
> gives you both structural and dynamic information in the same
> computational model.  And the latter is clearly needed for verification.
>
> On my wiki, I will be using the same creative commons license as on your
> wiki.  Once that is posted on my wiki, may I go ahead and quote from
> your emails using that same license?

Sure.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com