Re: [myhdl-list] delta cycles

[Jan D. <ja...@ja...>]

On 04/19/2012 09:10 AM, Thomas Heller wrote:
> Please consider a standard counter, something like this:
>
> def Counter(clock, count):
>       @always(clock.posedge)
>       def logic():
>           count.next = count + 1
>       return logic
>
> When this counter is simulated, count changes a delta cycle after
> the positive clock edge.  When traceSignals is used to write a VCD file,
> gtkwave shows that the count changes exactly at the same time as the
> clock edge.  This is confusing (at least in more complicated cases) in
> the timing diagram.

This is typical in the zero-delay RTL methodology: delta
cycles are a way to define causality within zero time.

I think most RTL designers cope with it (at least I did)
by developing a "clocks are special" mindset.

In fact, clocks are the only signals where such confusion is
possible. Therefore, I think measures such as a default delay
for all signals are overkill (and can lead to other types
of confusion).

I once saw a waveform viewer that allowed to visualize
delta cycles, but also here I think that is overkill.

If it is really a problem, I think the best way would be
solve it a the waveform viewer level, e.g. by moving
a clock trace backwards a little. But I am thinking
aloud, don't know if there are waveform viewers that
can do this.

Jan

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