Re: [myhdl-list] Restrictions for conversion

[Norbo <Nor...@gm...>]

Just wanted to provide a more highlighting example about the more general  
support of indexed constants if the array is initialized
in the verilog or vhdl code, especially about using multiple indices in  
the same expression:

   from myhdl import *

   def TOP(out1,in_data,in_addr):
       aListSig=[Signal(intbv(i)[8:]) for i in range(10)]
       @always_comb
       def comb_logic():
	  out1.next=aListSig[3]*3+aListSig[in_addr]*in_data

       return comb_logic


   def test_bench():
       sig1=Signal(intbv(0)[8:])
       in_data=Signal(intbv(0)[8:])
       in_addr=Signal(intbv(0)[8:])
       instanc_top=TOP(sig1,in_data,in_addr)

       #interval = delay(10)
       @instance
       def stimulus():
	  in_data.next=0
	  in_addr.next=0
	  yield delay(1)
	  print "Value1 is: ",sig1,"  Value2 is: ",in_data
	
	  in_data.next=2
	  in_addr.next=6
	  yield delay(1)
	  print "Value1 is: ",sig1,"  Value2 is: ",in_data
	
	  raise StopSimulation

       return  stimulus,instanc_top


   sim = Simulation(test_bench())
   sim.run(20)
   a,b,c = [Signal(intbv(0)[8:]) for i in range(3)]
   toVHDL(TOP,a,b,c)
   toVerilog(TOP,a,b,c)


Of curse this doesnt get mapped into ram, but the code is synthesisable  
and the netlist-viewer seems to show
a good result.
In the patch i posted previously i noticed an error i made:
The verilog code is not synthesisable if the list of signals is only used  
in reading, because then the toVerilog conversion
defines the list of signals with the "wire" keyword ( in the case above   
"wire [7:0] aListSig [0:10-1];" )
but it is not possible to use the "initial block" with the wire keyword.
so i changed it in this case to "reg" (in the case above  "reg [7:0]  
aListSig [0:10-1];")
I just appended the new patch.



greetings

Norbo