Re: [myhdl-list] Restrictions for conversion

[Norbo <Nor...@gm...>]

> As you are aware the use cases supported by MyHDL are RAM and ROM and
> examples for each and descriptions can be found here:
>
> http://www.myhdl.org/doc/0.7/manual/conversion_examples.html#ram-inference

I am actually not particular happy with this example because it is  
asynchron.

The following statment from [page14 ,  
http://www.altera.com/literature/hb/qts/qts_qii51007.pdf] kind of nails it,
and from my point of view it is not only true for altera devices.

"""Altera recommends using synchronous memory blocks for Altera designs.  
Because
memory blocks in the newest devices from Altera are synchronous, RAM  
designs that
are targeted towards architectures that contain these dedicated memory  
blocks must
be synchronous to be mapped directly into the device architecture. For  
these devices,
asynchronous memory logic is implemented in regular logic cells.
Synchronous memory offers several advantages over asynchronous memory,
including higher frequencies and thus higher memory bandwidth, increased
reliability, and less standby power."""



> In the past discussions the Altera recommended guidelines for RAM and
> ROM instantiation has been referenced.
> http://www.altera.com/literature/hb/qts/qts_qii51007.pdf.
>
>  From my experience tool specific pragmas or init files are used to
> pre-init RAMS in the FPGA vendor tools.  The guidelines for "specifying
> initial memory contents at power-up" is described start at section
> 11-32, which seem to suggest the same (.mif file).  But it does go on to
> describe a method for initializing, using an initial block in Verilog
> and a function in VHDL.  To get to an actual synthesizable approach it
> appears the initial values would not be enough?

The initial values for the array signal are enough for a synthesizable  
approach.
The Function with is used in the VHDL code is just another way which can  
be used to give the
signals in the array there initial values in a more procedural way (for  
vhdl). If you have the procedure
wich gives the values in python, you can write the initial values in vhdl  
to the array directly.
The "specifying initial memory contents at power-up"


> One of the reasons why initial values has not been implemented (it is on
> the todo list,
> http://www.myhdl.org/doku.php/dev:tasks#initial_values_suppot) is that
> it was observed that Quartus did not support initial value support in
> Verilog.  There would be a mis-match between the Verilog conversion and
> VHDL conversion.

I just can say that i use quartus v11.1 and i dont see this limitation  
there.
But this is probably not satisfactorily if someone uses a older version.

There is this another open task:
http://www.myhdl.org/doku.php/dev:tasks # More general support of indexed  
constants

If the  array of signals is initialized with values (also in the vhdl an  
verilig code)
  you can then use it also as a indexed "constant" value
in a more general way, this signal can  be used everyvere where like a  
normal signal.
if you never write to this signal it is just like a constant.


greetings
Norbo