Re: [myhdl-list] delta cycles

[Christopher F. <chr...@gm...>]

On 4/19/12 7:36 AM, Thomas Heller wrote:
> Am 19.04.2012 10:22, schrieb Ben:
>> On Thu, Apr 19, 2012 at 09:10, Thomas Heller<th...@ct...>   wrote:
>>> Please consider a standard counter, something like this:
>>>
>>> def Counter(clock, count):
>>>       @always(clock.posedge)
>>>       def logic():
>>>           count.next = count + 1
>>>       return logic
>>>
>>> When this counter is simulated, count changes a delta cycle after
>>> the positive clock edge.  When traceSignals is used to write a VCD file,
>>> gtkwave shows that the count changes exactly at the same time as the
>>> clock edge.  This is confusing (at least in more complicated cases) in
>>> the timing diagram.
>>>
>>
>> The solution I found that suited the most my need for this feature was
>> to alter the following line:
>>
>> http://hg.myhdl.org/cgi-bin/hgwebdir.cgi/myhdl/file/7a860a7fb408/myhdl/_Signal.py#l86
>>
>> And change the default value of delay from None to 1
>>
>> The reasoning behind that is that is that you almost never want this
>> setting to be set per Signal, you want it project-wide or you're gonna
>> be stucked in inconsistency loops ... This has for unique consequence
>> to make the VCD easier to debug. The generated code will look exactly
>> the same.
>
> Since I'm using factory functions to create my signals I can get a
> similar effect by changing their 'delay=' default value.  Except if
> MyHDL decides to create signals behind my back ;-).
>
>> The drawback of this method is that you have to set the duration of
>> your clock(s) accordingly so that your system be stable before the
>> next clock rises.
>
> Yes, it would be nice to be able to specify delay values smaller than
> 1ns; see my other post about the timescale.
> Probably I should patch myhdl.traceSignals to report a timescale of
> 1ps to the vcd file, and get used to specify delay values in ps.
>
> Thanks,
> Thomas
>
>

I think there could be a long and interesting conversation if this 
visual "delay" should be used or not.  In both Verilog/VHDL the default 
behavior is the no delay.  You have to explicitly state the delays in 
the assignments.

MyHDL is unique in that the MyHDL package is the HDL (the syntax and 
compiler to describe hardware behavior) and the simulator.  In my mind a 
better proposal, might be, additional arguments/methods to provide 
information to the simulator.  E.g. what is the *precision* in absolute 
time and should a _global_ propagation delay be used.

This would allow the HDL description to remain agnostic of absolute time 
and building in prop-delays that don't model anything other than a 
visual cue.

Regards,
Chris