Re: [myhdl-list] MyHDL timescale

[Oscar D. D. <osc...@gm...>]

El Thu, 19 Apr 2012 08:55:54 +0200
Thomas Heller <th...@ct...> escribió:

> MyHDL uses 'steps' as time unit.  When it writes VCD files with 
> traceSignals, one time unit is defined as 1ns.

Like you said, a step is the time unit; in practice you can assign
implicitly any time length for that step. The important thing is that a
step is the smallest time interval that can be modelled in the
simulation. 

For example, I can define a clock source with delay() calls, with a
frecuency of 10 steps, 50% duty cycle:

@instance
def clk_gen():
    while True:
        clk.next = 0
        delay(5)
        clk.next = 1
        delay(5)

I think the problem is that there isn't an explicit time unit for a
MyHDL step. In the previous example, I can say the clock frecuency is
100MHz, assuming a time step of 1ns. Or 100GHz, assuming 1ps as time
step.

I think it's a good idea to explicitly define the time length of a
simulation step, but not as a required feature. This feature can be
useful to do some asserts that require a time interval check, but it
isn't useful for RTL design.

Also, note that explicit time intervals are not supported for synthesis,
in the practice they are used only for testbenches.

Finally, the code that generates VCD files has the time unit fixed at
1ns. Maybe a small patch can be written to allow custom definition of
this time unit.

> 
> Considering the speed of todays logic, this is very coarse.
> 
> I would find it convenient to be able to specify sub-nanosecond
> delays as floats, and to make the timescale written into the
> vcd files configurable.

Personally I see float delays as excessive complex and useless for
event-based simulation. A better solution is to convert those float
delays to integer multiples of the time step.

> 
> Would this be an idea for MyHDL? Opinions?
> 
> Thanks,
> Thomas
> 
> 
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Oscar Díaz
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